When the electronic design automation (EDA) industry began creating standards for specifying and simulating digital electronic circuits, power management was relatively simple because most integrated circuit (IC) blocks operated on a single supply voltage. Hardware description languages thus provided no power management capabilities. Later designs used clock gating controls and multiple level-shifted supply voltages for different circuit blocks for basic power strategies. Different power domains could be simulated and verified with some largely straightforward extensions to the digital design methodology. In this description, a power domain is a collection of circuit elements that are typically powered in the same way, placed together in a physical circuit implementation, and powered by the same power rails.
Power management is however becoming increasingly important for meeting critical design constraints as integrated circuit designs increase in complexity and as battery-powered consumer devices dominate the marketplace. New design techniques have been developed to manage both static and dynamic power consumption. For example, back-bias control methods that raise transistor voltage thresholds and reduce leakage currents are now common.
These new techniques generally involve various new circuit components specifically for power-related circuit behavior. For example, power controllers and isolation cells may logically and/or electrically isolate a shut-down power domain from powered-up power domains. Level shifters may translate signal voltages from one power domain to another. Retention registers may store data to facilitate fast transitions from a power-off state to a power-on state. Power management logic may control the states and voltages of the supplies provided to the supply network, and may control the states of power switches that are part of the supply network.
Power-aware circuitry is therefore becoming more complex and difficult to manage. Designers are thus increasingly incorporating power awareness into designs as early in the design process as possible by consolidating the desired “power intent” or power management constraints for a circuit design into a single power specification. Design tool vendors have therefore adopted a standardized power specification format called Unified Power Format (UPF) that defines the syntax and semantics used to express power intent in power-aware electronic design tools. UPF is the popular name of the Institute of Electrical and Electronics Engineers (IEEE) 1801 standard; in both this description and colloquially in the design community, the IEEE1801 standard is synonymously referred to as UPF. (UPF is an exemplary but non-limiting power specification format; the Common Power Format (CPF) for example is also known to those of ordinary skill in the circuit design art.)
A UPF specification may generally define how to create a supply network to supply power to each circuit block, how the individual supply nets behave with respect to each other, and how logic functionality is extended to support dynamic power switching. A UPF specification may for example describe the voltage level shifting, driver or receiver isolation, power or ground switching, and state retention insertion constraints that are required for low power operation. UPF enables portability of power intent across a variety of commercial design tools throughout an entire design, analysis, and verification flow. UPF also defines the relationship between the power intent captured in its format and design intent captured via other formats (e.g., standard cell libraries).
While UPF has greatly aided power-aware digital design, challenges remain for applying UPF concepts to mixed-signal designs, which are among the fastest growing market segments in the electronics and semiconductor industry. Most system-on-chip designs today are mixed-signal, with more complex analog circuit blocks becoming more popular and also increasingly containing digital control logic. Adding power management to a mixed-signal design involves analyzing the design to determine which power supplies provide power to each logic element, and if drivers and receivers are in different power domains, inserting power-management cells as required to ensure that neither logical nor electrical problems result if the two power domains are in different power states. Mixed-signal circuit designers thus require verification methodologies that can accurately validate the interfaces and interactions between analog and digital domains.
Mixed-signal power-aware circuit design verification is additionally challenging because it may encompass both analog and digital circuit blocks described at different levels of abstraction. Circuit blocks may for example be represented in schematics, SPICE netlists, analog behavioral models, or via purely digital models described in various widely-used design languages. Digital circuit blocks may even be replaced with analog circuit block representations for increased simulation accuracy in some cases. Such replacement is becoming more common to better describe the actual electrical dynamics of power supply networks than is possible with simple fixed-value supplies.
Proper verification of modern power-aware mixed-signal circuits therefore demands not only coordinated simulation of both analog and digital circuit blocks in various representations, but also intuitive coordination of different power domains across an entire design hierarchy. A need thus exists for more fully dynamic interoperation between analog and digital circuit blocks in mixed-signal simulations involving multiple power domains. Accordingly, the inventors have developed a novel way to help circuit designers and design tool vendors more reliably design and dynamically test the operation of such ICs.